To respond to demands for reducing the power consumption of semiconductor integrated circuits (LSI) in recent years, it has been proposed to control the power supply voltage dynamically to deal with the variability in operation frequencies of LSI's and processes and to supply the minimum limit of voltage enabling an LSI to operate normally.
In a power supply voltage control apparatus adopting such a so-called variable power supply voltage control system, as shown in FIG. 26, in order to monitor the delay time of a critical path of the LSI 1, for example, a monitor circuit having a characteristic between a power supply voltage and delay equivalent to that of the critical path is provided, and the power supply voltage is controlled so that the signal propagation speed of the monitor circuit 2 enters a predetermined appropriate range.
Specifically, the power supply voltage control apparatus shown in FIG. 26 includes an input signal generation circuit 3 for generating an input pulse S1 to the monitor circuit 2 and a reference pulse S2 for delay detection, a delay detection circuit 4 for comparing the phases of an output pulse S3 obtained by propagation of the input pulse S1 by the monitor circuit 2 with the reference pulse S2, and a power supply voltage control circuit 5 for receiving the detection result of the delay detection circuit 4, generating a new power supply voltage by this, and switching the power supply voltage that had been supplied to the LSI 1 and the monitor circuit 2 to the new power supply voltage.
In an actual power supply voltage control circuit 5, for example, a voltage generation circuit 6 is configured by a DC—DC converter, and a processor or other control circuit 7 controls the program.
FIG. 27 gives views of various signal waveforms during operation of the power supply voltage control apparatus.
Here, FIG. 27A shows the input signal S1 (input pulse) of the monitor circuit 2 generated by the input signal generation circuit 3.
FIG. 27C shows the reference signal S2 (delay detection input) generated by the input signal generation circuit 3.
Further, FIG. 27B and FIG. 27D show the output signals S3A and S3B (monitor output A, B) output by propagation and delay of the input signal S1 in the monitor circuit 2. Among these, the monitor output S3A of FIG. 27B shows the case where the delay of the monitor circuit 2 is smaller than the reference value, while the monitor output S3B of FIG. 27D shows the case where the delay of the monitor circuit 2 is larger than the reference value.
In addition, M-DLV in FIG. 27B and FIG. 27D indicates a delay value of the monitor circuit, L-DLV a lacking delay value, and E-DLV an excess delay value, respectively, while the D-DLV in FIG. 27C indicates a desired delay value.
FIG. 28 is a flow chart showing the operation routine of the power supply voltage control apparatus.
Below, the operation of the power supply voltage control apparatus of FIG. 26 will be explained with reference to the waveform diagram of FIG. 27 and the flow chart of FIG. 28.
First, at step ST1, the input signal generation circuit 3 acting as a pulse generation circuit for example generates the input pulse (input signal) S1 and the delay detection input (reference pulse) based on an input system clock.
The input pulse S1 and the reference pulse S2 may be periodic signals having a constant phase difference or something like one-shot pulses or may be periodic signals of a duty ratio of 50%. It is sufficient that the frequency be lower than the system clock to a certain extent and that there be a constant delay value between them.
The reference pulse S2 is directly sent to one input of the delay detection circuit 4, while the input pulse S1 is delayed by a certain time in the monitor circuit 2 and then sent to the other input of the delay detection circuit 4.
Then, at step ST2, the delay detection circuit 4 detects the signal delay of the monitor circuit 2 based on the pulse S2 that does not pass the monitor circuit 2.
For example, it detects if the rising edge of the pulse of the output signal (monitor output) S3 of the monitor circuit 2 is earlier or later than the rising edge of the reference signal S2.
If the result of the delay detection, as shown in FIG. 27B, if the signal delay of the monitor circuit 2 is smaller than a lower limit of an appropriate range defined by the reference pulse S2, at step ST3, the control circuit 7 issues a request to lower the supplied voltage, and the voltage generation circuit 6 generates a lower power supply voltage VDD′ and switches it with the power supply voltage VDD supplied until then.
Conversely, as shown in FIG. 27D, if the signal delay value of the monitor circuit 2 is larger than an upper limit of the appropriate range, at step ST4, the control circuit 7 issues a request to increase the supplied voltage, and the voltage generation circuit 6 generates a higher power supply voltage VDD′ and switches it with the power supply voltage VDD supplied until then.
On the other hand, if the signal delay value is in the appropriate range, at step ST5, the power supply voltage VDD supplied so far is maintained.
The delay detection and the voltage control are carried out each time the reference pulse S2 is input, while feedback control is performed constantly.
The reference pulse S2 defines the upper limit of the appropriate range. Immediately after the delay value becomes larger than the reference pulse S2, the operation of increasing the supplied voltage is executed. On the other hand, the delay detection output includes information enabling determination of the magnitude of the excess delay, so the control circuit 7 issues a request for decreasing the supplied voltage when the delay value is smaller than a time obtained by subtracting a certain delay margin from the rising edge of the reference pulse S2.
In the power supply voltage control apparatus, the monitor circuit 2 is given a characteristic between a power supply voltage and delay equivalent to that of the critical path in the semiconductor circuit of the LSI 1. Therefore, it is possible to control the power supply voltage VDD to track the voltage level of the minimum limit of voltage required so that normal operation can be secured by the critical path plus a certain margin. Due to this, the power consumption is suppressed to the minimum limit.
In addition, in the conventional power supply voltage control apparatus, control feedback is made to operate in the minimum time required from the time when the delay detection circuit 4 detects a delay of the monitor circuit 2 so as to obtain a high control response.
In this conventional power supply voltage control apparatus, the delay value of the reference signal S2 relative to the input signal S1 is a constant, for example, one period's worth of the system clock signal. Because the delay value of the reference signal S2 is required to be set in the range where the delay value of the monitor circuit 2 changes, in the past, it was necessary to redesign even the input signal generation circuit 3 acting as a pulse generation circuit for each monitor circuit 2. As a result, this had become one factor increasing the burden in design and development of power supply voltage control apparatuses.
On the other hand, the monitor circuit 2 used in the conventional power supply voltage control apparatus had been designed to obtain a characteristic between a power supply voltage and delay equivalent to that of the critical path of an LSI. Therefore, when the delay value of the critical path of an LSI was large, the conventional monitor circuit for reproducing the delay characteristic included a large number of gate elements etc. and became large in size. Therefore, if the area of the power supply voltage control apparatus was large and this apparatus was integrated into an LSI, the cost of the LSI ended up rising.
Further, in the above power supply voltage control apparatus, for example, the output of a DC—DC converter or other source for supplying the power supply voltage sometimes fluctuates for a very short time because of noise etc. In this case, the signal propagation speed of the monitor circuit 2 receiving the supplied power rises for a while. As a result, the control circuit 7 issues a request for decreasing the power supply voltage.
After the power supply voltage is detected, however, it takes a certain amount of time before the control actually works, so when a power supply voltage lower than before is output by the voltage generation circuit 6 receiving the request of the control circuit 7, the variation in the power supply voltage sometimes already calms down. In this case, the power supply voltage has been lowered even though was not necessary, so the power supply voltage supplied to the semiconductor circuit is liable to fall below the minimum operating voltage required for the circuit to operate normally.
To lower this risk, it is enough to set a certain margin for the minimum operating voltage of the level of the control target of the power supply voltage. This voltage margin, for example, is defined by the difference of the amount of delay detected by the delay detection circuit 4 during normal operation and the delay serving as a reference for the start of control.
The minimum operating voltage of a semiconductor circuit can change due to the ambient temperature of the surroundings, but even if the minimum operating voltage changes, if tracking the change at all times using a level added with a sufficiently large constant margin as a control target of the power supply voltage, it is possible to prevent the operating voltage of the semiconductor circuit from becoming lower than the lower limit.
If the margin of the power supply voltage is made too large, however, the inherent effect of the power supply voltage control apparatus, that is, to supply the minimum limit of power supply voltage required so as to reduce the power consumption, ends up being weakened.
The condition required in a monitor circuit 2 in an apparatus configured as shown in FIG. 26 is that it be configured to give a desired delay value becoming a delay value equal to that of the critical path.
As a method for configuring such a monitor circuit, there is the method in which the critical path of a target circuit is extracted for configuration or the method in which a multistage string of delay elements is used for configuration.
However, in the former method in which the critical path of the target circuit itself is extracted for configuration, it is extremely difficult to extract a complicated critical path from a target circuit itself by path analysis. The critical path extracted by such work does not always match the critical path of a target circuit actually formed. In addition, work of extracting a critical path from the massive results of path analysis results is liable to lead to a longer design period.
Further, in the method in which a multistage string of delay elements is used for configuration, the strings of delay elements cannot always reproduce the critical path of the target circuit. Further, if preparing a plurality of multistage strings of delay elements differing in characteristics, the size of the circuit increases.
From this point of view, a circuit configuration of a monitor system which has general use, keeps the increase of the circuit scale to a minimum, and enables flexible and efficient design is considered necessary.